With the introduction of advanced applications and services and broader-band information networks in recent years, a larger capacity and a higher write speed have been required simultaneously of a flash memory as a semiconductor non-volatile memory element. In particular, the requirement for a larger-capacity flash memory has been growing far faster than the advancement of microfabrication technologies.
To providing a larger capacity, an approach of reducing the physical size of an element and another approach of storing a plurality of bits in one element and thereby reducing a per-bit area have been made from different directions. The former approach of reducing the physical size of the element is made by optimizing the structure of a memory element. As an example of the approach, there can be listed IEEE Technical Digest of International Device Meeting (see Non-Patent Document 1) As a conventional multi-bit technology for storing a plurality of bits of information in one element, a multi-level technology which prepares a plurality of levels to store 2 bits in each of cells has been used primarily. A multi-state technology for storing 2 bits in each of elements by storing electrons in spatially discrete places within one element by using the discrete memory effect of silicon nitride or the like has also been proposed recently. As a conventional example of the former multi-level multi-bit technology, there can be listed IEEE International Solid-State-Circuit Conference (see Non-Patent Document 2). As an example of the latter multi-state multi-bit technology, there can be listed Extended Abstract of the 1999 International Conference on Solid State Devices and Materials (see Non-Patent Document 3). Examples of the technology for positively forming two places in which charges are to be stored are disclosed in Patent Documents 1, 2, and 4.
A description will be given to a higher write speed. For a write operation to a single element, a writing method using the Fowler-Nordheim (F-N) tunneling effect has been used. Although a write operation to an element using the F-N tunnel effect requires a long time, a write speed which is high to a degree is obtainable when measured on a chip level since write operations to a large number of memory elements can be performed simultaneously. In accordance with the F-N tunneling method using a high voltage, however, the area of a peripheral circuit cannot be reduced so that the chip area is increased, i.e., cost is increased, which makes it difficult to provide a large capacity.
As structures which enable a high-speed write operation without the provision of an isolation, a virtual ground array in which a diffusion is shared by adjacent elements and a memory device using a high-efficiency writing method termed source side injection (SSI) have been proposed. The method is disclosed in, e.g., Patent Document 3.
There has also been proposed recently an element structure which achieves both a reduction in element size and a high-speed write operation at the same time (see, e.g., Non-Patent Document 4). The structure uses a field isolation technology for electrically isolating adjacent elements from each other in a MOS structure instead of an isolation region composed of silicon dioxide which occupies a large proportion in element area. By the field isolation technology and the multi-level multi-bit technology, a reduction in the element area has been achieved. By implementing a split gate structure using a gate used for the electric isolation, a high-efficiency write operation in accordance with a method termed source side injection (SSI) is performed and a high-speed write operation is thereby enabled.
[Patent Document 1]
JP-A No. 230332/2001
[Patent Document 2]
JP-A No. 237330/2001
[Patent Document 3]
U.S. Pat. No. 6,344,993
[Patent Document 4]
U.S. Pat. No. 5,949,711
[Non-Patent Document 1]
IEEE Technical Digest of International Device Meeting 2000, p. 767
[Non-Patent Document 2]
IEEE International Solid-State-Circuit Conference 1996, pp.32–33
[Non-Patent Document 3]
Extended Abstract of the 1999 International Conference on Solid State Devices and Materials, Tokyo 1999, pp.522–523
[Non-Patent Document 4]
IEEE Technical Digest of International Electron Device Meeting 2001, p.29
As described above, the demand for a larger capacity has been growing far faster than the advancement of microfabrication technologies. To meet the demand, the multi-bit storage technology which stores 2 bits in one element has thus far been introduced. However, a greater demand for a larger capacity has been placed by the market, which requests the storage of 3 or more bits.
Problems encountered by the multi-level multi-bit technology will be described herein below. To impart a uniform write or erase characteristic to each of a plurality of memory elements under the condition under which the width of the distribution of the threshold voltage of the element should be reduced compared with the case of 1-bit storage, it is required to perform a write or erase operation while repeating a verify operation which performs reading after the application of a pulse. In the case of performing write/erase operations to a plurality of elements, therefore, a period of time several to several tens of times longer than an average charge injection (release) time for a single element becomes necessary. Thus far, a technology which prepares four threshold voltage levels and stores 2 bits of information in one element has been used practically. With overheads resulting from the verify operation, however, it is significantly difficult to achieve both the storage of 8 or more levels (3 bits of) information and high-speed write/erase operations at the same time.
Problems encountered by the multi-state multi-bit technology will also be described herein below. The conventional multi-state multi-bit storage accomplishes multi-bit storage by a method termed channel hot electron (CHE) injection, in which charges are injected independently in charge storage regions at the vicinity of the source and drain edge of a memory element. Since the method uses only two types of charge storage regions which are the source-edge region and the drain-edge regions, the maximum amount of information that can be stored is naturally 2 bits. In terms of performing a high-speed write operation, the CHE allows a high-speed operation to a single element. However, since the proportion of currents injected into the charge storage regions relative to currents flowing between the source and drain is low, i.e., a writing efficiency is low, it is necessary to allow large currents to flow between the source and drain. Since the number of elements to which write operations can be performed simultaneously is limited by the limited current driving ability of a peripheral circuit, it is difficult to achieve a high write speed on a chip level.
To enable a high-speed write operation on a chip level, it is necessary to simultaneously perform write operations to a large number of elements. To enable simultaneous write operations to a large number of elements, it is essential to perform high-efficiency write operations and reduce a leakage current flowing during the write operations. Although the use of the SSI writing method enables a high-efficiency write operation, the SSI method normally requires a high voltage of 3 V or more to be applied between the source and drain. Even if an element is scaled down through miniaturization, the voltage is not scaled down. This is because electrons in the channel should be accelerated till they reach a state having an energy higher than a physical amount of an energy barrier (3.2 eV) between a gate oxide film and silicon. The voltage is also applied between the source and drain of an element adjacent to a write target element. To reduce the leakage current flowing during the write operation, it is necessary to reduce a leakage current in the element adjacent to the write target element.
The leakage current can be reduced by using the conventional physical isolation region. However, since the dimensions of the physical isolation region cannot be reduced normally, element miniaturization is difficult. Even when the field isolation is used, if the gate length is reduced as a result of miniaturization, a leakage current is increased disadvantageously by a punch-through effect. As a result, it becomes difficult to perform a high-speed write operation.